1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM), and in particular to precharging techniques.
2. Discussion of the Related Art
Memory devices are widely used in many electronic products and computers to store data. A memory device includes a number of memory cells. A DRAM device operates by storing charge on a capacitor at each memory location. Ultimately, the capacitor loses the charge over time and therefore needs to be periodically refreshed to its original level, a 1 or 0. All of the memory cells must be refreshed within one refresh period, tREF, which may be for example 64 ms. Refreshing is accomplished by doing a row access for every row in the memory device. In a refresh cycle, all of the capacitors in one or more rows are first read, and then written back to, restoring full charge to the capacitor. An open row of a bank must be precharged prior to being refreshed. The rows and columns of a DRAM device may be partitioned into multiple banks to reduce the large DRAM arrays into smaller segments.
As the number of storage cells per memory bank, and the number of memory banks per device increases, the number and duration of refresh commands issued by a memory controller also increases. Since all of the open banks must be closed (precharged) before a refresh command can be issued, the number of “precharge all” commands issues by a memory controller also increases. This ultimately results in a precharge and refresh overhead that unacceptably impacts the performance of normal memory accesses. The main precharge overhead is the penalty paid in closing pages that might otherwise be left in their open, lower latency state. A secondary penalty is that as the number of banks grows, additional clocks may be added to the time required for a precharge.
In order to reduce the precharge overhead, it may be desirable to precharge a fraction of the banks for each precharge command. This approach may be called partial multibank precharge. With a given precharge command, a fraction of the banks may be either simultaneously or sequentially precharged. To maximize overall system performance it may be more desirable to precharge banks simultaneously in order to minimize the time that bank resources are tied up. A partial multibank precharge is particularly useful when combined with a partial multibank refresh. Only the particular fraction of the memory device that is to be refreshed is precharged, with the remaining fraction left in its current state.
Additionally, as DRAM devices become larger, the time required from the refresh command until the next command, the AUTO-REFRESH command period tRFC, grows substantially. The impact of increased tRFC is an increase in the read latency of read requests that occur during the refresh itself. Again, a row must be precharged prior to being refreshed. Therefore, the time required to precharge a row, tRP, may also lead to an increase in the read latency of read requests that occur during the precharge. For a DRAM device with a larger number of banks, there will be times when the read and write activity is skewed to one portion or another of the DRAM. Performance may be improved if precharges and refreshes are done opportunistically to the portion of the DRAM not in use, with concurrent read or write operations to the remaining portion of the DRAM.
As microprocessor speed increases, memory access speed must also increase. At the same time, the number of memory banks per memory device continues to increase, for example from four banks to eight banks to sixteen banks. Using current DRAM technology, the “precharge” command causes one bank of the DRAM to be precharged, and the “precharge all” command causes all of the banks of the DRAM to be precharged. This also requires the closing of all open pages, i.e., open rows. With multi-bank memories more locations need to be precharged at any given time, and precharging draws more power in a shorter time for the larger multi-bank memories. Therefore, either the current required for an all-bank precharge operation will be roughly double, for example, for eight banks as compared to four banks, or the time required to perform the precharge operation will be somewhat longer as compared to the four bank precharge. Thus, current spikes can cause significant noise problems on the power line during a precharge operation, and a longer precharge/refresh will increase the latency of any reads that are waiting for the precharge/refresh to complete. Current DRAM devices do include a precharge command that is given to just one bank of the DRAM. But when refreshing four or eight banks of a DRAM, it would be very inefficient to issue four or eight of these single bank precharge commands ahead of the refresh command.
Accordingly, current precharge protocols limit precharging to one row at a time in order to control precharging noise. What is needed is a partial precharge command that precharges a fraction of the banks of a DRAM device per command.